Matt Venn and the TinyTapout community are very friendly to beginners. I highly encourage people to participate in the upcoming TinyTapeout 3 run. They even have a visual editor, if people don't want to mess with Verilog and prefer direct drawing of logic gates: https://wokwi.com/projects/339800239192932947
My design was rather simple , compared to others I saw. I designed a tool to explore the Hamming error-correcting code.
What if you prefer direct drawing of the mask layers?
We have FPGAs for (most) logic stuff, but what if I wanted a tiny, power-efficient RF (Wi-Fi or GPS for instance) chip?
There are very few things that are more complex than toys which fit in that space. It's primarily a learning opportunity, not a hack to build a product.
Also, most of the hard work in Wi-Fi and GPS modules is not in receiving the binary radio signal but in the protocols to decode it. For wifi, the 802.11 protocol would require your PHY to provide at the very least the orthogonal frequency-division multiplexing, but you're probably expecting something closer to a Wiznet chip that provides the fundamental stack available from eg. the lwIP project.
As I understand it there will be a TT3 and the way pins happen will likely greatly change - more pins and faster everything
That opens the door to less conventional stuff, such as CMOS imagers, memories, RF/Analog designs, etc. Obviously the available space and I/O are going to be limitting factors.
Regarding Wi-Fi, I was thinking of some of the RF frontend for a project such as . I am not extremely knowledgeable about RF, so that would be a learning opportunity. I imagine it to be mostly carrier generation and multiplexing, the higher layers are doable on an off-the-shelf FPGA.
That said, Wi-Fi is a simple target, but maybe not the most interesting one. That's the first full-custom application example I thought of.
A 6502 with 3.5k transistors might fit comfortably in that size: https://news.ycombinator.com/item?id=11703995
A 4004 has 2.3k transistors and may also fit.
Regarding the other comment about there only being 14 pins, if I was determined to try putting an early CPU replica in there, I would try multiplexing the pins. The 4004 is already in a 16-pin package, with 2 of those being power and ground.
For instance if you had programmed the ASIC with a function that replaced something done in software, how do you divert the data from the relevant step over to the ASIC and back again? Can they keep up with CPUs (or is it the other way round?)
It's a toy to demystify the ASIC design process. You can get a bare chip produced or for more money, get the same chip already soldered down onto a PCB. There's a good render of it in this article: https://www.eenewseurope.com/en/tinytapeout-boost-for-open-s... - it has a 7-segment display and some pin breakouts.
If you were to build an ASIC to replace a general purpose computing function, you'd usually either synthesize PCI Express or USB functionality into your design, design a breakout PCB to interface with the bus, and then write a device driver to interface with whatever endpoints your device presented, or add a microcontroller of some kind in "front" of the device that talked PCI Express or USB and translated into a "lower level" chip communication method like I2C, SPI, or even raw parallel address/data/clock lines.
Low-latency is achieved with a Carry Look-Ahead Adder and includes subtraction.
O(n^2) naïve multiplier design, whereas O(n^1.58) is easily achieved and extendable to MAC capabilities.
Then there's a divider unit.
Pipelining with branch prediction.
Superscalar with reservation stations.
Hyperthreading (slack time virtual cores).
And add your mask easter egg here.
I don't think it's fair to knock it like that. This isn't going inside some industrial project. This is a hobbyist who went from zero(!) to ASIC.